Design and Implementation of CVNS Based Low Power 64-Bit Adder

Abstract

In this project, design of a mixed-signal 64-bit adder based on the Continuous Valued Number System
(CVNS) is presented. The 64-bit adder is generated by cascading four 16-bit Radix-2 CVNS adders. Truncated
Summation of the CVNS digits reduced the number of required interconnections in the system, which in turn reduces
design complexity, power and hardware costs. This adder can perform one 64-bit, two 32-bit, four 16-bit additions on
demand for media signal processing applications. The compact and low-power design of the CVNS adder is suitable for
multimedia applications. This system implements an algorithm for Digital Systems which requires less number of
interconnections due to truncation summation. The synthesize 64-Bit CVNS adder using Cadence RTL Encounter has a
timing slack 7ps, power consumption of about 98.55 fW with the core area of 3995 μm2