DESIGN OF VITERBI ALGORITHM USING PCAG

Abstract

The Viterbi algorithm, an application of dynamic programming, is widely used for estimation and detection problems in digital communications and signal processing. It is used to detect signals in communication channels with memory, and to decode sequential error- control codes that are used to enhance the performance of digital communication systems. In architecture of Viterbi algorithm, we are utilizing scheme of polar code address generator which is based on the low complexity and low latency. The main benefit of this proposed system is that it gives reliable requirements and as well as performance degradation. For the motive of bench mark we are improving the both application specific integrated circuit and field programmed gate array. Depend upon the reliability objectives and performance degradation tolerance, the proposed system is utilized.