A Novel Architecture for a High-Speed Multiply and Accumulate Circuit Using a Three-Operand Binary Adder

Abstract

The three-operand binary adder is a core element in cryptographic and pseudorandom bit generator algorithms, 
where it performs the modular arithmetic those algorithms depend on. The carry-save adder (CS3A) is the technique 
normally used for this, but its ripple-carry second stage gives a propagation delay of O(n), so the delay grows linearly 
with word length. Using a parallel prefix two-operand adder such as Han-Carlson (HC3A) in two stages reduces the 
critical path but costs additional hardware. This paper implements an alternative architecture that performs three
operand addition through pre-computed bitwise addition followed by carry-prefix computation logic, reducing the 
adder delay to O(log₂ n) while using less area and dissipating less power than HC3A. The four-stage structure 
comprises bit-addition logic, base logic, propagate-generate logic and sum logic. A 16-bit version of the adder was 
described in Verilog, and used to build a multiply-and-accumulate (MAC) unit with 8-bit inputs and a 16-bit output, 
the arrangement used in digital filters and neural network accelerators, where the same multiply-add is executed 
repeatedly and its latency sets the throughput of the whole datapath. The design was implemented and simulated in 
Xilinx tools, and the synthesis results show it achieving the lowest area-delay and power-delay products among the 
three-operand adder techniques compared.