1.
Semal Sekhar Mummana, T. Pattalu Naidu, K. Sandhya, K. Sai Srinivasu, T. Ramya, R. Anusha. A Novel Architecture for a High-Speed Multiply and Accumulate Circuit Using a Three-Operand Binary Adder. ijmrr. 2025;15(2):427-434. Accessed September 16, 2026. https://ijmrr.com/index.php/ijmrr/article/view/762