MR. D. VEERANNA, DR. K. AMIT BINDAJ, DR. A. VENKATESWARLU, N. SRINIVAS RAO, MRS. K. YOJANA. Design and Implementation of CVNS Based Low Power 64-Bit Adder. INTERNATIONAL JOURNAL OF MANAGEMENT RESEARCH AND REVIEW, India, v. 12, n. 3, p. 1–8, 2022. Disponível em: https://ijmrr.com/index.php/ijmrr/article/view/416. Acesso em: 17 sep. 2026.