SEMAL SEKHAR MUMMANA; T. PATTALU NAIDU; K. SANDHYA, K. SAI SRINIVASU, T. RAMYA, R. ANUSHA. A Novel Architecture for a High-Speed Multiply and Accumulate Circuit Using a Three-Operand Binary Adder. INTERNATIONAL JOURNAL OF MANAGEMENT RESEARCH AND REVIEW, India, v. 15, n. 2, p. 427–434, 2025. Disponível em: https://ijmrr.com/index.php/ijmrr/article/view/762. Acesso em: 16 sep. 2026.