Semal Sekhar Mummana, T. Pattalu Naidu, and K. Sandhya, K. Sai Srinivasu, T. Ramya, R. Anusha. 2025. “A Novel Architecture for a High-Speed Multiply and Accumulate Circuit Using a Three-Operand Binary Adder”. INTERNATIONAL JOURNAL OF MANAGEMENT RESEARCH AND REVIEW 15 (2): 427-34. https://ijmrr.com/index.php/ijmrr/article/view/762.