[1]
Mr. D. Veeranna, Dr. K. Amit Bindaj, Dr. A. Venkateswarlu, N. Srinivas Rao, Mrs. K. Yojana, “Design and Implementation of CVNS Based Low Power 64-Bit Adder”, ijmrr, vol. 12, no. 3, pp. 1–8, Jul. 2022, Accessed: Sep. 17, 2026. [Online]. Available: https://ijmrr.com/index.php/ijmrr/article/view/416