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Semal Sekhar Mummana, T. Pattalu Naidu, K. Sandhya, K. Sai Srinivasu, T. Ramya, R. Anusha. A Novel Architecture for a High-Speed Multiply and Accumulate Circuit Using a Three-Operand Binary Adder. ijmrr [Internet]. 2025 Jun. 27 [cited 2026 Sep. 16];15(2):427-34. Available from: https://ijmrr.com/index.php/ijmrr/article/view/762